The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for implementing a self-referencing read operation for phase-change random access memory (PCRAM) devices.
Dynamic Random Access Memory (DRAM) integrated circuit arrays have been existence for several years, with their dramatic increase in storage capacity having been achieved through advances in semiconductor fabrication technology and circuit design technology. The considerable advances in these two technologies have also resulted in higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
A DRAM memory cell typically includes, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a first voltage is stored on the capacitor to represent a logic HIGH or binary “1” value (e.g., VDD), while a second voltage on the storage capacitor represents a logic LOW or binary “0” value (e.g., ground). A basic drawback of a DRAM device is that the charge on the capacitor eventually leaks away and therefore provisions must be made to “refresh” the capacitor charge, otherwise the data bit stored by the memory cell is lost.
The memory cell of a conventional Static Random Access Memory (SRAM), on the other hand, includes, as basic components, an access transistor or transistors and a memory element in the form of two or more integrated circuit devices interconnected to function as a bistable latch. An example of such a bistable latch is a pair of cross-coupled inverters. Bistable latches do not need to be “refreshed,” as in the case of DRAM memory cells, and will reliably store a data bit indefinitely so long as they continue to receive supply voltage. However, such a memory cell requires a larger number of transistors and therefore a larger amount of silicon real estate than a simple DRAM cell, and draws more power than a DRAM cell. Like a DRAM array, an SRAM array is also a form of volatile memory in that the data is lost once power is removed.
Accordingly, efforts continue to identify other types of memory elements that are capable of storing data states, that do not require extensive refreshing, and that are non-volatile in nature. Recent studies have focused on resistive materials that can be programmed to exhibit either high or low stable ohmic states. A programmable resistance element of such material could be programmed (set) to a high resistive state to store, for example, a binary “1” data bit or programmed to a low resistive state to store a binary “0” data bit. The stored data bit could then be retrieved by detecting the magnitude of a readout voltage supplying a current switched through the resistive memory element by an access device, thus indicating the stable resistance state it had previously been programmed to.
Phase Change Random Access Memory (“PCRAM” also referred to as “PRAM”) is an emerging non-volatile memory technology which stores data using phase change materials (such as Ge—Sb—Te (GST) alloys) having a programmable electrical resistance that changes with temperature. Other compositions such as GeSb4, (including substitution/addition of other elements) are also possible for the phase change materials. Individual phase change elements (PCE) are thus used as the storage cells of a memory device. The state of an individual PCE is programmed through a heating and cooling process which is electrically controlled by passing a current through the PCE (or a discrete heating element in proximity to the PCE) and the resulting ohmic heating that occurs. Depending upon the specific applied temperature and duration of heating applied to the PCE element, the structure is either “set” to a lower resistance crystalline state or “reset” to an amorphous, higher resistance state. Essentially, there is no practical limit to the number of times a PCE element may be programmed from the crystalline state to the amorphous state and vice versa.
The changing of the phase of a PCE typically requires a high temperature (e.g., above 200° C. to 900° C. depending on material properties), as can be obtained by Joule heating from current flowing through the phase change material or discrete resistor. When the phase change material is heated above its melting temperature to thereafter be quickly cooled, the phase change material becomes amorphous to store a data bit of “1.” Alternatively, when the phase change material is heated above its crystallization temperature and maintained at that temperature for a predetermined time before cooling, the phase change material becomes crystalline to store a data bit of “0.”
More specifically, FIG. 1 is a graph illustrating the exemplary thermal cycling operations of a phase change material used as a PCE storage cell. As is illustrated, a first thermal cycling operation includes a “RESET” pulse for converting the PCE from crystalline to amorphous form, and a second thermal cycling operation includes a “SET” pulse for converting the PCE from amorphous to crystalline form. During the RESET pulse, the temperature of the PCM is raised above its melting temperature (Tm), followed by a rapid quench over a short time t1. As a result of the rapid quench, the disordered arrangement of atoms of the PCM due to the melt is retained. Thus, the PCM is left in an amorphous, high resistive state after the RESET pulse. During the SET pulse, the PCM is annealed at a lower temperature with respect to the melting temperature, and for a longer time t2 with respect to t1. This process enables the amorphous form to crystallize into a lower resistive state.
A key aspect to the feasibility of PCM memory technology is the ability to design large-scale arrays so as to allow random access of millions of bits. This may be done, for example through an array of PCEs, each gated by associated access transistors using a matrix of word lines (WL) (e.g., formed from a polysilicon gate material) and bit lines (BL) (e.g., formed with metal interconnect material). The current passing through the PCE may be controlled via the bit line (BL) and/or word line (WL). However, due to the parasitic capacitance of the bit lines, resistance variations in the bit lines, variations in the access transistors, and other process variations, the cell current (and thus power) used in the writing process can have variations, thus leading to a distribution of resistance values for both low and high resistance states.
Further complicating the matter of design is the operating temperature range of the chip. For example, if one PCE cell is written when the ambient temperature is −25° C. and another cell is written when the ambient temperature is +85° C., the resulting resistances for the same logic state may be significantly different from one another. Conversely, the resistances for opposite states may actually be substantially close in value to one another. Even with the use of temperature compensation circuits for both write and read operations, the apparent distributions will broaden and the signal margin will shrink.
Historically, the reading of a PCE memory cell is implemented by applying either a current or voltage and measuring a resulting voltage or current respectively, and then comparing the measured current/voltage against a known reference value. The known reference value may be digitally set or generated on chip through averaging a low and high value, or multiplying a low or high value by a factor. Regardless, each of these techniques is fundamentally the same, in that a signal by the cell to be read is compared to a fixed reference level. Again, if the temperature or processing conditions vary such that there is a large variation in the cell resistance values for both crystalline amorphous states, it becomes difficult to ensure a single fixed reference value is appropriate for proper cell state detection.
One way to avoid the use of a single reference level is to utilize the so-called “twin cell” design, in which two PCE devices per bit are used. One of the cells is written low and the other high, depending on the logical state. During a compare, if cell A is high and B is low then the output of a sense amplifier (and hence the logical state of the cell) is a 1, and conversely if A is low and B is high then the sense amplifier output is a 0. While this alleviates the need of having one reference fit level fit all the bits, it comes at the cost of the array efficiency (using two PCEs per bit) to be roughly half that of a non twin cell chip. Accordingly, it would be desirable to be able to implement a more improved, robust PCE read technique in a manner that does not adversely impact the array efficiency.